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First International Workshop on High-Performance Reconfigurable Computing Technology and Applications (HPRCTA'07)

Held in conjunction with SC07
Reno, NV, November 11, 2007

High-Performance Reconfigurable Computing (HPRC) based on the combination of conventional microprocessors and field-programmable gate arrays (FPGA) is a new and rapidly evolving computing paradigm that offers a potential to accelerate computationally intensive scientific applications beyond of what is possible on today's mainstream HPC systems. The academic community has been actively investigating this technology for the past several years and the technology has proven itself to be practical for a number of HPC applications. Many of the HPC vendors are now offering or are planning to offer various HPRC solutions. The goal of this workshop, co-located with SC 2007, is to provide a forum for academic researchers and industry to discuss the latest trends and developments in the field, and to set a research agenda for the upcoming years on the use of field-programmable gate array technology in high performance computing.

Important dates

  • Papers due: September 15, 2007
  • Notification of acceptance: October 15, 2007
  • Final camera-ready manuscripts due: November 1, 2007
  • Workshop: November 11, 2007

Program Committee

  • Duncan Buell, USC
  • Tarek El-Ghazawi, GWU
  • Kris Gaj, GMU
  • Alan D. George, CHREC
  • Martin Herbordt, Boston University
  • Volodymyr Kindratenko, NCSA (conference contact)
  • Eric Stahlberg, OpenFPGA
  • Olaf Storaasli, ORNL

Workshop Sponsors
NSF Center for High-Performance Reconfigurable Computing (CHREC) National Center for Supercomputing Applications OpenFPGA

 

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