Reconfigurable Systems Summer Institute
Sponsored by NCSA and OSC

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2005 RSSI Speaker Abstracts

The Future of Reconfigurable Computing: A "Small Matter of Programming"
Duncan Buell
Professor and Chair, Department of Computer Science and Engineering, University of South Carolina

Monday, July 11
9:00 am
Room 1025, Beckman (Auditorium)

Programmable logic devices have been used for "real computing" purposes, with varying degrees of success, for nearly two decades. We argue that one problem hampering a steady success record has been the use of many hardware platforms and just as diverse a set of software support tools, with relatively little technology that builds on past work to make the task of application development easier for the next application.

We will review the history of reconfigurable computing in this light and present arguments for why success has been infrequent. We will also argue that a change has occurred in reconfigurable computing that suggests reasons to hope for much greater success in the future, in part because several vendors are now offering serious computer *systems* that incorporate reconfigurable resources.

Much more important to success, in our opinion, is the ability to refer to the use of these systems as *programming* and not hardware design. The application development environment has been the Achilles heel of reconfigurable computing since the early days, but there are reasons to believe that dramatic improvements are occurring due to environments, tools, and compilers with which software developers will feel comfortable. We will survey recent events that we believe justify our optimism.



A Computational Physicist's View of Reconfigurable High Performance Computing
Vincent Natoli
Co-founder, Stone Ridge Technology

Monday, July 11
10:30 am
Room 1025, Beckman (Auditorium)

Field programmable gate arrays present an alternative approach to algorithmic computation using spatial computing in contrast to traditional CPU solutions based on von Neumann architectures. By implementing algorithms in hardware, taking advantage of pipelining and fine-grained parallelism, FPGAs can offer significant application acceleration.

This talk will explore the strengths and weaknesses of reconfigurable computing from the perspective of an application programmer. It will include the historical development of HPC hardware, challenges facing HPC today, technology trends, scaling laws, barriers to adoption and the role that FPGAs may play in the near future. It will address the theoretical performance of FPGA's for computation across a range of metrics including IEEE floating point implementation, bandwidth limitations, power consumption and economics.



The Cray XD1 Computer and its Reconfigurable Architecture
David Strenski
Application Analyst, Cray, Inc.

Monday, July 11
1:00 pm
Room 1025, Beckman (Auditorium)

As microprocessors approach the end of their technology curves, they have moved to putting more processors on the same chip. This improves the compute density of cluster type machines, but makes it harder to get optimal performance out of the entire system. What does the programmer do to improve single-processor performance? One solution is to move to a different technology. A microprocessor has a fixed instruction set and typically performs one 64-bit addition and multiplication per clock, with the clock running at a few gigahertzs. Field programmable gate arrays (FPGAs) that are attached to the Cray XD1 nodes allow the user to build custom logic and effectively build a hardware device to perform the calculations, laying down hundreds of functional units. The FPGAs are not without limitation though; the FPGA's clock frequency runs an order of magnitude slower than the microprocessors and the amount of chip real estate limits the depth and width of the calculation that can be perform. FPGAs are also very complicated to program. This talk will cover the Cray XD1 architecture and explain how the FPGAs are intergrated into the system. It will also step through the execution of a simple example showing how the data flows between the Opteron, FPGA, and memory. Finally the talk will give some results of application speed-up on some real applications using FPGAs.



Implementing Algorithms in FPGA-Based Reconfigurable Computers Using C-Based Synthesis
Doug Johnson
Technical Marketing Manager, Celoxica, Inc.

Monday, July 11
2:00 pm
Room 1025, Beckman (Auditorium)

FPGAs in reconfigurable computers are used to accelerate integer-based, wide datapath and massively parallel computation. Moreover, the current generation of FPGA devices can enable fast parallel floating-point calculations in many applications. Managing the complexity of FPGA hardware design in a predominantly software-driven application sector is a particular challenge for the development of reconfigurable computing applications. We will describe a software-compiled system design methodology using C-synthesis and hardware-software partitioning tools that overcomes these challenges. Unlike traditional hardware design or block based design entry, these technologies provide a practical and familiar design flow for HPC application developers to explore the acceleration of software systems using FPGAs.

Following the presentation will be a demonstration of Celoxica's DK Design Suite of software tools. Celoxica's tools and methodology fuse system verification, hardware-software co-design and SystemC/C-language synthesis into a single flow targeting FPGA implementation. Celoxica's C- and SystemC-based tools perform direct synthesis to Xilinx, Altera and Actel FPGA netlists and also generate synthesizable VHDL and Verilog HDL code for verification ASIC synthesis. Celoxica's tools enable simulation of hardware and software portions of the design in a common environment that includes multiple models and languages such as C, SystemC, Handel-C, VHDL and Verilog.



Software: The Next Direction for Reconfigurable Computing
Stefan Möhl
Chief Research Officer and Co-Founder, Mitrion

Monday, July 11
3:30 pm
Room 1025, Beckman (Auditorium)

The current practices in the field of Reconfigurable Computing are almost exclusively rooted in traditional hardware development practices. The tools used, the development techniques employed and the problem domains addressed with FPGAs are currently locked squarely in the realm of hardware design. We will examine some of the underlying mechanisms that historically have led to this situation, and question the validity of those mechanisms as being predominant with regards to large, modern FPGAs.

Looking at current systems incorporating large FPGAs, including supercomputers with FPGAs fully integrated as computational units, we will contrast the practices of hardware design with those of software programming. We will argue that a paradigmatic shift of the employment of FPGAs is required to fully benefit from the possibilities of these systems. This shift will include the methods of programming of FPGAs, the tools and techniques used, the problem domains addressed, the supporting systems employed and the patterns of use for these systems.

We will present the first steps taken in this direction by Mitrionics. A system is presented, expected for public release in October, on top of which FPGAs can be programmed at the actual software level. By abandoning traditional mainstays of hardware design, such as designing for a target clock-speed or manually determining the length of pipelines, we hope to achieve a level of abstraction equal to that in parallel programs written in FORTRAN or C. When programming the Mitrion system, focus is shifted from implementation to description. The Mitrion system strives for a level of abstraction where code is written for readability, clarity and maintainability, in contrast to hardware designs made for the exact positioning of data in the FPGA during each clock-cycle. In so doing, many of the traditional problem domains addressed by FPGA systems are abandoned. On the other hand, many new problem domains are opened up.

The principles behind this system, the basics of the programming language Mitrion-C and examples of program code will be presented.



Field Programmable Gate Arrays - Power in Future HPC Systems
Eric A. Stahlberg
Senior Systems Manager, Ohio Supercomputer Center
Adjunct Instructor Computer Science, Franklin University

Tuesday, July 12
8:30 am
Room 1025, Beckman (Auditorium)

Field programmable gate arrays are expected to play an increasing role in future high-performance computing systems, adding a new dimension of parallelism to exploit in high-level applications. While the motivations for developing systems balanced with FPGA technology are clarifying, the path to delivering applications on these platforms is much less resolved. Current and future challenges facing the porting, development and availability of applications for these blended architectures will be discussed. Efforts already under way to address these hurdles will also be highlighted.



Starbridge Solutions to Supercomputing Problems
Esmail Chitalwala
Starbridge Systems, Inc.

Tuesday, July 12
11:00 am
Room 1025, Beckman (Auditorium)

Reconfigurable computing presents an exciting and challenging domain in supercomputing. It demands creativity not only from an application standpoint, but also requires innovative design and development toolsets used in reconfigurable computing. This presentation discusses the applicability of Starbridge technologies to supercomputing applications on reconfigurable systems and aims to address potential issues and concerns faced by application designers.



Application Development on SRC Reconfigurable Computing Systems
Jeffrey P. Hammes
Daniel S. Poznanovic
SRC Computers, Inc.

Tuesday, July 12
1:30 pm
Room 1025, Beckman (Auditorium)

This presentation discusses Reconfigurable Computing technology. The enabling hardware and the software tools are discussed and demonstrated. FPGA chips and the source of their ability to deliver high performance are presented. The SRC Computers system architecture and programming environment are reviewed with example codes used to demonstrate program development and performance achieved on the SRC system. Participant will leave with an understanding of the sources of performance in a reconfigurable system, the nature of programming, and unique optimizations that are possible in such systems.



Is it Time for Von Neumann and Harvard to Retire?
Allan Cantle
President and CEO, Nallatech

Tuesday, July 12
3:30 pm
Room 1025, Beckman (Auditorium)

The last 12 months have seen the computing world wake up to the fact that, just maybe, the industry can't "keep its feet on the innovation table" and rely on ever increasing clock frequencies and decreasing feature sizes to double computing performance every 18 months. Suddenly they are scratching their heads and asking themselves, "is there a better way?"

Meanwhile, a group of mavericks has been touting a revolution in computing for over a decade, their calls falling largely on deaf ears. The advent of FPGAs has allowed custom compute solutions to have the flexibility and programmability of a microprocessor while approaching the efficiency and performance of a custom compute ASIC.

These two camps are now coming together and the next decade promises to be the most invigorating and exciting for computing architectures for over 30 years.

This presentation will explore the history and commercial realities of FPGA computing today. It will explore:

  • FPGAs as co-processors
  • FPGAs as main processors
  • Distributed computing versus massively parallel computing
  • Optimizing spatial and temporal demands of computing problems
  • Heterogeneous versus polymorphic computing
  • Coarse grain vs fine grain architectures

The mavericks are often still considered to be the lunatic fringe by the traditional computer community. The facts will speak for themselves and the presenter's personal vision will also be given, including his view on the fate of the Von-Neumann and Harvard architectures. However, in reality, the user community will dictate the direction of tomorrow's computing world. Let's all enjoy the ride!



Reconfigurable Computing Made Easy!
Michael Babst
President and founder, DSPlogic, Inc.

Tuesday, July 12
4:30 pm
Room 1025, Beckman (Auditorium)

The state of reconfigurable computing (RC) today is reminiscent of the state of digital signal processors (DSP) about 15 years ago. DSP technology enabled amazing speed improvements, but it was very difficult to harness these benefits. High-level language tools were in the early stages of development and designers were forced to develop costly assembly code and real-time operating systems to fulfill the promises of DSP. Today, RC developers are forced to battle Hardware Description Languages (HDL), synthesis tools, and timing issues to truly fulfill the promises of FPGA-based RC. Fortunately, optimized FPGA core libraries help to fulfill this promise, but often still leave difficult system integration issues to solve.

We will discuss an RC design methodology that, today, can simultaneously provide extremely rapid algorithm development while delivering efficient use of FPGA resources for maximum application acceleration. The Reconfigurable Computing I/O (RCIO) API is a basic CPU-FPGA interface that simplifies both CPU and FPGA application development while providing high-bandwidth, low-latency communications, and portability over multiple platforms. The functionality and performance of the RCIO interface will be described in terms of applications that have been successfully accelerated using the API. An example design flow will demonstrate rapid application development with direct algorithm-to-FPGA bitstream functionality for the Cray XD1.



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