Fall 1993 access

CM-5 Enhancements Attract Friendly Users

by Michael Welge, Research Programmer, Computational Mathematics and Computer Science Team

A year ago the first CM-5 hardware shipping crates arrived at NCSA. Since that time, the CM-5 friendly user community has experienced several hardware changes that have greatly enhanced the viability of the system for Grand Challenge scientific computations.

The CM-5, Connection Machine (Model 5), is designed by Thinking Machines Corp. (TMC), Cambridge, MA.

Hardware Enhancements

NCSA's CM-5 initially supported 512 RISC processors. This basic processing node consisted of a microprocessor, memory subsystem, and a CM-5 network interface all connected to a standard 64-bit bus. The SPARC microprocessor, running at 32 MHz, is capable of 22 MIPS and 5 Mflops.

Today, NCSA's CM-5 has been optionally configured with the Data- path floating point system (also referred to as DASH, or vector units). There are four vector units per node, all running under control of the SPARC microprocessor. One memory and two arithmetic operations (mult, add) can be performed per vector unit per clock cycle. The vector unit clock rate is 16 MHz, and peak performance is 128 Mflops per node. This upgrade increased the aggregate theoretical performance from 2.5 to 64 Gflops and the DRAM memory from 8 to 16 Gbytes.

The addition of the 100 Gbyte Scalable Disk Array (SDA) in mid-April provides an extremely high-performance, highly expandable disk storage system comprised of Disk Storage Nodes. The basic Disk Storage Node--which provides 9.2 Gbytes of storage, a peak bandwith over 17 Mbytes per second, and 25 MIPS of processing power--comprises a controller built on a SPARC processor, a network interface, a large disk buffer, four advanced SCSI controllers, and eight 3.5" hard disk drives. These SDA Disk Storage Nodes-- analogous to the computational processing nodes--are directly connected to the CM-5 internal network.

This direct connection enables each Disk Storage Node to contribute not only to storage capacity but also to I/O performance. The number of Disk Storage Nodes in the SDA can be increased or decreased, thereby achieving an I/O system matched to the performance and capacity needed for the user's application. NCSA's CM-5 SDA consists of 12 Disk Storage Nodes that provide 100 Gbytes of storage at I/O bandwidths of up to 132 Mbytes per second sustained.

CM-HIPPI Arrives Soon

NCSA's user community will experience increased transfer rates from the CM-5 to other supercomputer systems when the CM-HIPPI device is ready later this year. CM-HIPPI is an integrated system that receives CMFS files system commands from the CM-5 control processor. The CM-HIPPI contains a CPU, disk drives, a VME bus, and HIPPI I/O interface modules. The CM-HIPPI connects directly to the CM-5 network to provide 1 gigabit aggregate bandwidth.

In mid-September a TMC CM-5 testbed system with a HIPPI interface was installed at NCSA. Its goal is to support UIC/NCSA's CAVE (Cave Automatic Virtual Environment) demo at Supercomputing '93. It will also allow for a smooth integration of HIPPI into NCSA's CM-5 production system.

CM-HIPPI team members are Randy Butler (group leader), Joseph Godsil, Vijay Rangarajan, Von Welch, and Paul Zawada.

Application Research Efforts

Many users took advantage of the CM-5 friendly user period to make use of the increased performance of the distributed memory CM-5. Many of those same users continue computing on the CM-5, which entered into production in May.

Watch for reports of some Grand Challenge research in the next issue of access, which will focus on Grand Challenge research.

access * Fall 1993 * NCSA